Funding Round Highlights
SambaNova Systems is reportedly negotiating a financing round of more than $350 million. The lead investor is expected to be Vista Equity Partners, marking the firm’s first foray beyond pure enterprise‑software investments. Other participants include Cambium Capital and Intel, which may contribute up to $150 million.
The round follows stalled acquisition talks with Intel (a $1.6 billion offer) and comes after SambaNova exceeded its 2025 sales targets, fueling renewed investor interest.
SN40L Chip Architecture
The flagship SN40L inference chip houses 1,040 cores fabricated on TSMC’s 5‑nanometer process. Core clusters are split across two silicon dies mounted on a CoWoS interposer that also integrates high‑bandwidth memory (HBM) for rapid model data access.
- 638 trillion BF16 calculations per second
- Two‑die layout with interposer‑based HBM
- Optimized kernel placement to minimize data‑movement latency
Performance Techniques: Operator Fusion & On‑Chip Networking
The SN40L employs operator fusion, merging hundreds of operations into a single step to cut unnecessary computation. While this creates intense on‑chip data traffic, SambaNova’s built‑in network automatically resolves bottlenecks, preserving both speed and power efficiency.
Product Portfolio: SambaStack & SambaManaged
The chip is delivered within an air‑cooled system called SambaStack, which bundles 16 inference accelerators, networking hardware, and power‑management modules. The platform can handle AI models up to 5 trillion parameters.
SambaManaged, launched last July, reduces deployment time to 90 days and has already secured contracts with four data‑center operators, including a sovereign cloud campus in Scotland slated for >2 GW capacity.
Market Impact and Outlook
Strong customer momentum, coupled with the new funding, positions SambaNova to accelerate product roll‑outs and expand its presence in hyperscale data centers. Institutional interest from Vista Equity and Intel underscores confidence in the company’s differentiated chip architecture and its potential to shape the next generation of AI inference workloads.