Overview
Recent rumors from leaker HXL on X indicate that AMD’s next‑generation Zen 6 architecture will feature a larger L3 cache and a new 12‑core CCD layout, aiming to improve multi‑threaded performance while keeping the cache‑to‑core ratio consistent with previous generations.
CCD Architecture Changes
Zen 6 is expected to move away from the traditional 8‑core CCD used in Zen 4 and Zen 5. The proposed layout is:
- 12 cores per CCD
- Unified L3 cache shared across all 12 cores
This is a significant shift from earlier designs where eight cores were split into two CCX clusters that communicated via Infinity Fabric.
L3 Cache Details
According to the leak, the new CCD will pair the 12 cores with a 48 MB L3 cache, preserving the roughly 4 MB per core ratio seen in Zen 2‑5.
- Zen 2: 2 × 4‑core CCD, 16 MB L3 (8 MB per CCD)
- Zen 3‑5: 8‑core CCD, 32 MB L3 (4 MB per core)
- Zen 6: 12‑core CCD, 48 MB L3 (4 MB per core)
Process Node and Performance Gains
AMD plans to fabricate Zen 6 on TSMC’s N2 2 nm process. The node promises:
- ~15 % higher transistor density
- Up to 15 % performance uplift at the same power envelope compared to the previous N4 node
These improvements, combined with the larger core cluster, should boost multi‑threaded workloads.
Potential X3D Variants
While no official X3D models have been announced for Zen 6, AMD’s recent success with 3D‑VCache suggests that future X3D versions could add even more L3 cache on top of the already larger 48 MB baseline.
Conclusion
If the leaks prove accurate, Zen 6 will represent a major architectural shift for AMD, delivering a 12‑core CCD, a 48 MB L3 cache, and a move to the 2 nm N2 process. These changes are poised to enhance multi‑threaded performance and set the stage for next‑generation X3D processors.